1. Field of the Invention
The present invention generally relates to a cross-point type switch using a common buffer memory used in a transmission system, such as an ATM (Asynchronous Transfer Mode) transmission system or a high-bit-rate packet communication system in a broadband ISDN (Integrated Services Digital Network).
2. Description of the Prior Art
Standardization of an ATM transmission system has progressed recently as a transmission method of a next-generation broadband ISDN. It is desired that a device in conformity with such a transmission method be compact, of low energy consumption, and has a flexible communication capacity matchin various system structures.
In conventional technology, a shared buffer type switch and a cross-point type switch are known as switches suitable for advanced communication systems, as described above.
FIG. 1 shows a conventional shared buffer type switch. As shown in FIG. 1, the shared buffer type switch is composed of an input port group 1 consisting of N input ports #1, #2 . . . #N, N output ports #1, #2 . . . #N, a memory 3, N routing units 4, a multiplexer unit 5, a memory controller 6, and a demultiplexer unit 7.
The routing units 4 receive data, such as ATM data, received via the input port group 1, and determine paths to which the received data should be output. The multiplexer unit 5 changes the bit rates of the data from the routing units 4, and multiplexes the data synchronized with a clock signal different from a clock signal(s) with which the data are transferred via the input port group 1. The multiplexed data are written into the memory 3 under the control of the memory controller 6. The data are read out from the memory 3 under control of the memory controller 6. For example, the memory controller 6 writes data in the memory 3 and reads out data therefrom by an FIFO (First-In First-Out) procedure. The data read out from the memory 3 are output to the output port group 2.
The single memory 3 is used by a plurality of input ports, and is not required to have a large storage capacity. However, in order to multiplex data transferred via a plurality of input ports and write the multiplexed data into the memory 3, it is necessary to execute a phase adjustment procedure before the multiplexing process. As a result, a higher-access-speed memory is needed, as a larger number of input ports are used.
FIG. 2 shows an improvement in the structure shown in FIG. 1. In FIG. 2, parts which are the same as those shown in FIG. 1 are given the same reference numerals. The memory shown in FIG. 3 is divided into a plurality of memories (1)-(n). Hence, it becomes possible to separately store data into the memories (1)-(n), so that an increased memory access speed can be obtained.
FIG. 3 shows a conventional cross-point type switch. In FIG. 3, parts which are the same as those shown in the previously described figures are given the same reference numerals. The cross-point type switch shown in FIG. 3 includes the input port group 1, the output port group 2, an output controller 8, an expanded input port group 9 and an expanded output port group 10. Each of the expanded input and output port groups 9 and 10 includes N ports.
The output controller 8 determines an output port to which data received via the input port group 1 should be output. For example, if data received via input port #2 should be output to output port #N, the data is stored in a memory 3-2N, and then read out therefrom. In this manner, the data is transferred to the output port #N.
Normally, a plurality of cross-point switches are connected to provide a single switching system. If data received via input port #1 should be transferred to another cross-point switch at which the received data should be switched, the data is passed to output port #1 of the expanded output port group 10. If data received via expanded input port #2 should be transferred to output port #2, no data from the input ports #1-#N is transferred to output port #2 at this time. That is, under the control of the output controller, either data from the input port group 1 or data from the expanded input port group 9 is output to the output port group 2 at one time.
However, the switch shown in FIG. 2 needs a synchronizing process in order to synchronize the memories provided at the cross points with each other. Hence, the output controller 8 must execute a complex control procedure. In addition, the switch shown in FIG. 2 does not have an expandability because it cannot have any expanded input and output ports.
The cross-point switch shown in FIG. 3 has a disadvantage in that a large storage capacity is needed at each cross point. However, the cross-point switch has advantages in that the switch can operate at a low memory access speed, and input and output data can be asynchronous with each other. Further, the switch shown in FIG. 3 has an expandability because it has expanded input and output ports.
It is a general object of the present invention to provide a cross-point type switch having the advantages of the shared-buffer type switch and the advantages of the cross-point type switch.
The above object of the present invention is achieved by a cross-point type switch including a plurality of basic elements arranged in rows and columns so as to form a matrix arrangement of the basic elements. Each of the basic elements includes a plurality of input ports, output ports, expanded input ports and expanded output ports. A write/read part is connected to a common memory, and has the function of writing data into the common memory and reading out the data from the common memory. A selector part selectively outputs either data read out from the common memory or data from the expanded input ports to the output ports. The expanded output ports are directly connected to the input ports.